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exar corporation 48720 kato road, fremont ca, 94538 ? (510) 668-7000 ? fax (510) 668-7017 ? www.exar.com xr xrk39351 3.3v or 2.5v, 9-output pll clock driver november 2006 rev. 1.0.0 general description the xrk39351 is a low voltage pll based clock driver designed for high speed clock distribution applications. the xrk39351 has two reference clock inputs, one lvpecl and the other lvcmos. the ref_sel input selects clock input to be used as the pll?s reference source. the xrk39351 uses pll technology to frequency lock its outputs to the clock reference input. the divider in the feedback path will determine the frequency of the vco. the xrk39351 provides 9 lvcmos outputs that are separated into 4 banks. each of the separate output banks can individually divide down the vco output frequency. this allows the xrk39351 to generate a variety of output-to-input frequency ratios (1:1, 1:2, 1:4, 2:1 and 4:1). all outputs provide lvcmos compatible levels while driving 50 terminated transmission lines. the input reference clock can be directly applied to the output dividers bypassing the pll when pll_en input is pulled low. this is a test mode intended for system debug purposes. the xrk39351 has an output/input frequency range of 25mhz to 200mhz with the pll enabled and an input frequency range of 2mhz to 300mhz when the pll is disabled (test mode). features ? 9 lvcmos outputs (4 banks) ? 25 - 200 mhz output frequency range ? fully integrated pll ? 2.5v or 3.3v operation ? selectable reference clock input, lvcmos or lvpecl ? 150ps max output to output skew ? pin compatible with mpc9351 ? industrial temp range: -40c to +85c ? 32-lead tqfp packaging f igure 1. b lock d iagram of the xrk39351 pll ref fb 8 4 2 1 0 1 0 1 0 1 0 tclk fb_in pll_en sela selb selc oe qa qc 0 qc 1 1 0 pecl pecl r ef_sel vdd qd 4 qd 0 qd 1 qd 2 qd 3 q b 1 0 seld
xrk39351 xr 3.3v or 2.5v, 9-output pll clock driver rev. 1.0.0 2 product ordering information p roduct n umber p ackage t ype o perating t emperature r ange xrK39351CQ 32-lead tqfp 0c to +70c xrk39351iq 32-lead tqfp -40c to +85c f igure 2. p in o ut of the xrk39351 1 2 3 4 5 6 7 8 9 10111213141516 25 24 23 22 21 20 19 18 32 31 30 29 28 27 26 17 xrk39351 selc selb sela oe pecl agnd fb_in pll_en avcc vcc qd4 gnd qd3 qd2 vccqd gnd qc0 qc1 vccq c vccq d qd0 qd1 gnd ref_se l tclk gnd gnd qa qb vccqb seld pecl
xr xrk39351 rev. 1.0.0 3.3v or 2.5v, 9-output pll clock driver 3 pin descriptions n umber n ame t ype d escription 1 avcc power power supply for pll 2 fb_in input pull-down external pll feedback clock input 3 sela input pull-down selects divider value for bank a output 4 selb input pull-down selects divider value for bank b output 5 selc input pull-down selects divider value for bank c outputs 6 seld input pull-down selects divider value for bank d outputs 7 agnd power pll ground 8 pecl input lvpecl - pos differential reference clock 9 pecl input lvpecl - neg differential reference clock 10 oe input pull-down output enable/disable and device reset 11 vcc power power supply for core, inputs and bank a output clock 12, 14, 16, 18, 20 qd[4:0] output bank d clock outputs 13, 17, 21, 25, 29 gnd power ground 15, 19 vccqd power power supply for bank d output clocks 20, 22 qc[1:0] output bank c clock outputs 23 vccqc power power supply for bank c output clocks 26 qb output bank b clock output 27 vccqb power power supply for bank b output clock 28 qa output bank a clock output 30 tclk input pull-down lvcmos reference clock input 31 pll_en input pull-up selects pll or pll-bypass (test mode) operation 32 ref_sel input pull-down selects primary reference clock source
xrk39351 xr 3.3v or 2.5v, 9-output pll clock driver rev. 1.0.0 4 a. vcmr is the cross point of the differential input signal. t able 1: control input function table p in n ame 01 d efault ref_sel pecl clock inputs selected as reference tclk input selected as reference 0 pll_en pll is bypassed. test mode. tclk refer - ence source drives the divider select blocks pll enabled. normal operation. vco out - put drives the divider select blocks 1 sela bank a divider = 2 bank a divider = 4 0 selb bank b divider = 4 bank b divider = 8 0 selc bank c divider = 4 bank c divider = 8 0 seld bank d divider = 4 bank d divider = 8 0 oe outputs enabled outputs tri-stated, vco running at minimum frequency 0 dc c haracteristics (v cc = 3.3 + 5%, t a = -40 c to +85 c) s ymbol c haracteristics m in t yp m ax u nit c ondition v cmr a pecl clock inputs common mode range 1.2 v cc -0.9 v v pp pecl clock peak-to-peak input voltage 500 1000 mv v ih input voltage high 2.0 vcc+0.3 v v il input voltage low 0.8 v v oh output high voltage a 2.4 v i oh =-24ma v ol output low voltage a 0.55 0.30 v v i ol =24ma i ol =12ma z out output impedance 14-17 i in input leakage current + 150 ? v in =v cc or v in =gnd i cc_pll maximum pll supply current 3.0 5.0 ma av cc pin i cc maximum quiescent supply current 4 ma all v ccqx pins v tt output termination voltage v cc 2 v
xr xrk39351 rev. 1.0.0 3.3v or 2.5v, 9-output pll clock driver 5 . a. ac characteristics apply for parallel output termination of 50 to v tt . ac c haracteristics (v cc = 3.3 + 5%, t a = -40 c to +85 c) a s ymbol p arameter m in t yp m ax u nit c ondition f vco vco frequency 200 400 mhz f ref input reference frequency 2 feedback 4 feedback 8 feedback pll bypass 100 50 25 2 200 100 50 300 mhz pll_en = 1 pll_en = 1 pll_en = 1 pll_en = 0 f max max output frequency 2 feedback 4 feedback 8 feedback 100 50 25 200 100 50 mhz t ir /t if input rise/fall time 1.0 ns 0.8 to 2.0v f refdc input clock duty cycle 25 75 % t pd propagation delay - (spo, input clock to fb) tclk to fb_in pecl to fb_in -50 -25 150 325 ps ps pll locked pll locked t skew output-to-output skew 150 ps t jit(cc) cycle-to-cycle jitter (rms) 4 feedback 10 22 ps all outputs set to 4 t jit(per) period jitter (rms) 4 feedback 8 15 ps all outputs set to 4 t jit(i/o) i/o phase jitter (rms) 4 - 17 ps bw pll bandwidth 2 feedback 4 feedback 8 feedback 9.0-20.0 3.0-9.5 1.2-2.1 mhz mhz mhz dc output duty cycle 2 feedback 4 feedback 8 feedback 45 47.5 48.75 50 50 50 55 52.5 51.75 % % % 100 - 200mhz 50 - 100mhz 25 - 50mhz t lock maximum pll lock time 1.0 ms t or /t of output rise/fall time 100 1000 ps 0.55 to 2.4v t plz,hz output disable time 10 ns t phz,lz output enable time 10 ns
xrk39351 xr 3.3v or 2.5v, 9-output pll clock driver rev. 1.0.0 6 a. vcmr is the cross point of the differential input signal. dc c haracteristics (v cc = 2.5 + 5%, t a = -40 c to +85 c) s ymbol c haracteristics m in t yp m ax u nit c ondition v cmr a pecl clock inputs common mode range 1.2 v cc -0.6 v v pp pecl clock peak-to-peak input voltage 500 1000 mv v ih input voltage high 1.7 vcc+0.3 v v il input voltage low 0.7 v v oh output high voltage 1.8 v i oh =-15ma v ol output low voltage 0.6 v i ol =15ma z out output impedance 17-20 i in input leakage current + 150 ? v in =v cc or v in =gnd i cc_pll maximum pll supply current 3.0 5.0 ma av cc pin i cc maximum quiescent supply current 1 ma all v ccqx pins v tt output termination voltage v cc 2 v
xr xrk39351 rev. 1.0.0 3.3v or 2.5v, 9-output pll clock driver 7 . a. ac characteristics apply for parallel output termination of 50 to v tt . ac c haracteristics (v cc = 2.5 + 5%, t a = -40 c to +85 c) a s ymbol p arameter m in t yp m ax u nit c ondition f vco vco frequency 200 400 mhz f ref input reference frequency 2 feedback 4 feedback 8 feedback pll bypass 100 50 25 200 100 50 mhz pll_en = 1 pll_en = 1 pll_en = 1 pll_en = 0 f max max output frequency 2 feedback 4 feedback 8 feedback 100 50 25 200 100 50 mhz t ir /t if input rise/fall time 1.0 ns 0.7 to 1.7v f refdc input clock duty cycle 25 75 % t pd propagation delay - (spo, input clock to fb) tclk to fb_in pecl to fb_in -100 0 100 300 ps ps pll locked pll locked t skew output-to-output skew 150 ps t jit(cc) cycle-to-cycle jitter (rms) 4 feedback 10 22 ps all outputs set to 4 t jit(per) period jitter (rms) 4 feedback 8 15 ps all outputs set to 4 t jit(i/o) i/o phase jitter (rms) 6 - 25 ps bw pll bandwidth 2 feedback 4 feedback 8 feedback 4.0-15.0 2.0-7.0 0.7-2.0 mhz mhz mhz dc output duty cycle 2 feedback 4 feedback 8 feedback 45 47.5 48.75 50 50 50 55 52.5 51.75 % % % 100 - 200mhz 50 - 100mhz 25 - 50mhz t lock maximum pll lock time 1.0 ms t or /t of output rise/fall time 100 1000 ps 0.6 to 1.8v t plz,hz output disable time 12 ns t phz,lz output enable time 12 ns
xrk39351 xr 3.3v or 2.5v, 9-output pll clock driver rev. 1.0.0 8 a. absolute maximum continuous ratings are those maximum values beyond which damage to the device may occur. exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. absolute maximum ratings a s ymbol characteristics m in m ax u nit c ondition v cc supply voltage -0.3 4.6 v v in dc input voltage -0.3 v cc +0.3 v v out dc output voltage -0.3 v cc +0.3 v i in dc input current + 20 ma i out dc output current + 50 ma t s storage temperature -55 150 c general specifications s ymbol c haracteristics m in t yp m ax u nit c ondition v tt output termination voltage v cc 2 v mm esd protection (machine model) 200 v hbm esd protection (human body model) 2000 v lu latch-up immunity 200 ma c in input capacitance 4.0 pf inputs ja thermal resistance junction to ambient jesd 51-3, single layer test board jesd 51-6, multi layer test board 62.0 47 c/w c/w natural convection jc thermal resistance junction to case 14 c/w operating junction temperature 115 c f igure 3. o utput - to - output s kew t sk(o) the pin-to-pin skew is defined as the worst case difference in propagation delay between any similar delay path within a single device. v cc v cc 2 gnd v cc v cc 2 gnd t sk(o)
xr xrk39351 rev. 1.0.0 3.3v or 2.5v, 9-output pll clock driver 9 f igure 4. p ropogation delay (t (?) , static phase offset ) test reference f igure 5. o utput d uty c ycle (dc) f igure 6. i/o j itter f igure 7. c ycle - to - cycle j itter fb_in t (?) cclkx v cc v cc 2 gnd v cc v cc 2 gnd tp t 0 dc=t p /t 0 x 100% the time from the pll controlled edge to the non controlled edge, divided by the time between pll controlled edges, expressed as a percentage v cc v cc 2 gnd fb_in cclkx t jit(i/o) = |t 0 -t 1 mean | the deviation in t 0 for a controlled edge with respect to a t 0 mean in a random sample of cycles the variation in cycle time of a signal between adjacent cycles, over a random sample of adjacent cycle pairs t n t n+1 t jit(cc) = |t n -t n+1 |
xrk39351 xr 3.3v or 2.5v, 9-output pll clock driver rev. 1.0.0 10 f igure 8. p eriod j itter f igure 9. o utput t ransition t ime t est r eference the deviation in cycle time of a signal with respect to the ideal period over a random sample of cycles t 0 t jit(per) = |t n -1/f 0 | v cc =3.3v t of 2.4v 0.55v t or v cc =2.5v 1.8v 0.6v
xr xrk39351 rev. 1.0.0 3.3v or 2.5v, 9-output pll clock driver 11 package dimensions note: the control dimension is the millimeter column inches millimeters symbol min max min max a 0.055 0.063 1.40 1.60 a 1 0.002 0.006 0.05 0.15 a 2 0.053 0.057 1.35 1.45 b 0.012 0.018 0.30 0.45 c 0.004 0.008 0.09 0.20 d 0.346 0.362 8.80 9.20 d 1 0.272 0.280 6.90 7.10 e 0.0315 bsc 0.80 bsc l 0.018 0.030 0.45 0.75 0 7 0 7 32 lead thin quad flat pack (7 x 7 x 1.4 mm tqfp) rev. 2.00 24 17 16 9 18 25 32 d d 1 d d 1 b e a 2 a 1 a seating plane l c
xrk39351 xr 3.3v or 2.5v, 9-output pll clock driver rev. 1.0.0 12 notice exar corporation reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. exar corporation assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. charts and schedules contained here in are only for illustration purposes and may vary depending upon a user?s specific application. while the information in this publication has been carefully checked; no responsibility, however, is assumed for inaccuracies. exar corporation does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the li fe support system or to significantly affect its safety or effectiveness. products are not authorized for use in such applications unless exar corporation receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has been minimized; (b) the user assumes all such risks; (c ) potential liability of exar corporation is adequately protected under the circumstances. copyright 2006 exar corporation datasheet november 2006. reproduction, in part or whole, without the prior written consent of exar corporation is prohibited. revision history r evision # d ate d escription 1.0.0 november 2006 initial final release.

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